CP/M 50, a 50MHz 2x1 inch CP/M computer
The idea here was to design and build a small CP/M computer using readily available parts. This page provides an overview of the board design and software. Interested readers can find more detail in the schematic and source code referenced at the end of this page.
The images below show the top and bottom sides of the completed design. The board is 2 inches wide by 1 inch tall. The 4 wires connected to the board are for programming the Z8 microcontroller and will be removed after debugging is complete.
The design is built around a ZiLOG eZ80L92 processor running at 50MHz. System memory is provided by a single 128K, 12ns SRAM. Using 12ns SRAM allows the external bus to run with zero wait-states. Disk storage is provided by a microSD card connected to the L92's SPI bus that is clocked at 12.5Mb/s. A USB to UART bridge connected to one of the L92's UARTs provides connectivity to a serial console. A ZiLOG Z8 Encore XP microcontroller bootstraps the system by loading a bootstrap image, from its internal flash, into the L92's external SRAM using the ZDI debug interface of the L92. A 3.3V LDO regulator powers the system from the USB bus. Below is a block diagram of the system.
The board runs CP/M 2.2 that consists of a custom BIOS, or CBIOS, and the standard distribution of CCP and BDOS. The main functions of the CBIOS are to provide a console interface via one of the L92's serial ports and disk emulation via SPI and a microSD card. The microSD card provides four 8MB drives. Disk I/O performance is enhanced by the use of sector blocking and de-blocking algorithms. Terminal I/O makes use of the L92's 16-byte receive and transmit FIFOs.
Below are screen shots of the system boot message and several applications. Click on an image for a higher resolution shot.
|Boot Message||Ladder||SuperCalc2||WordStar||Zork I|
The "The Unofficial CP/M Web site" contains a wealth of information about Digital Research and CP/M. Various CP/M sources and manuals can be found there.